1. Field of the Invention
This invention relates to a semiconductor memory and more particularly, to a semiconductor memory having a sense amplifier which has a metal oxide semiconductor field effect transistor (MOSFET) as the main component and makes fast access possible.
2. Description of the Related Art
FIG. 1 is a block diagram of a conventional semiconductor memory having MOSFETs as the main component, and FIG. 2 is a circuit diagram showing a concrete example of the memory shown in FIG. 1.
With the conventional semiconductor memory as shown in FIGS. 1 and 2, a signal COJ from a memory cell block 4 is amplified by a sense amplifier 1 and sent to a differential amplifier 2 as an output signal SA. On the other hand, the differential amplifier 2 receives a reference signal RA from a reference amplifier 3. The differential amplifier 2 amplifies a difference signal between the output signal SA and reference signal RA and outputs it as a signal OUT1.
The sense amplifier 1 comprises, as shown in FIG. 2, an N-channel MOSFET Q1, a P-channel MOSFET Q2 which serves to operate as a load of the MOSFET Q1 and an inverter INV1. The N-channel MOSFET Q1 has the drain connected to an output end 1b of the sense amplifier 1 and the source connected to an input end 1a of the sense amplifier 1. To the drain of the MOSFET Q1, a power source voltage Vcc is supplied through the MOSFET Q2. The inverter INV1 has an input end connected to the input end 1a and an output end connected to the gate of the MOSFET Q1. To the source of the P-channel MOSFET Q2, the power source voltage Vcc is supplied through a power source end 1c . The gate and drain of the MOSFET Q2 are connected in common to the output end 1b. The sense amplifier 1 receives the input signal COJ from the memory cell block 4 through the input end 1a and sends the output signal SA through the output end 1b to the differential amplifier 2.
AN N-channel MOSFET MY1 is connected between the input end 1a of the sense amplifier 1 and a point 8 for connection to a digit line (a row line). The N-channel MOSFET MY1 is a Y-selector. Connected between the connecting point 8 and the ground G, is an N-channel enhancement MOSFET MB1 and an N-channel depletion MOSFET MB2, which are block decoders, and one memory cell block 4 connected in series.
The memory cell block 4 has 15 N-channel enhancement MOSFETs M1 to M15 and one depletion MOSFET M16 connected in series with each other. Each of these 16 MOSFETs M1 to M16 makes a memory cell. Though not shown here, a plurality of memory cell blocks, sense amplifiers and other related elements each having the same structure as in FIG. 2 are provided.
The sense amplifier 1 outputs one of different electric potentials Von and Voff as the output signal SA through the output end 1b to the differential amplifier 2 in accordance with whether a selected memory cell is in the conduction or non-conduction state.
Next, the operation of the sense amplifier 1 will be explained below.
If a selected memory cell of the memory cells M1 to M16 is under the conduction state, that is, for example, if a signal line Y1 connected to the MOSFET MY1 of the Y-selector, a signal line XB1 connected to the MOSFET MB1 of the block decoder and signal lines X1 to X15 connected respectively to the memory cells M1 to M15 are made at high levels and a signal line XB2 connected to the MOSFET MB2 of the block decoder and a signal line X16 connected to the memory cell 16 are made at low levels, the sense amplifier 1 sends a low level voltage Von to the differential amplifier 2 as the output signal SA.
The operation in this case is as follows; If the selected memory cell is in the conduction state, an electric current flows to the ground G and the electric potential of the input end 1a of the sense amplifier 1 is gradually lowered due to discharging. When the electric potential of the input end 1a becomes lower than the theoretical threshold voltage of the inverter INV1, the output of the inverter INV1 is switched from the low level to the high level, and the MOSFET Q1 is switched from the non-conduction state to the conduction state. As a result, the electric potential of the output end 1b of the sense amplifier 1 is switched from the high level to the low level, so that the sense amplifier 1 sends the low level potential Von to the differential amplifier 2 as the output signal SA. On the other hand, if the selected memory cell is under the non-conduction state, that is for example, if the signal lines Y1, XB1, X1 to X14 and X16 are made at high levels and the signal lines XB2 and X15 are made at low levels, the sense amplifier 1 sends the high level potential Voff to the differential amplifier 2 as the output signal SA.
The operation in this case is as follows; When the selected memory cell is in the non-conduction state, the electric potential of the input end 1a is at the low level, so that the MOSFET Q1 enters the conduction state by the operation of the inverter INV1. As a result, the connecting point 8 of the digit line is charged by the MOSFET Q2 through the MOSFET Q1 and MOSFET MY1. Accordingly, if an electric potential SD of the input end 1a is increased to exceed the theoretical threshold voltage of the inverter INV1, the output signal of the inverter INV1 is switched from the high level to the low level, and the MOSFET Q1 enters the non-conduction state. Therefore, the electric potential of the output end 1b of the sense amplifier 1 is charged by the MOSFET Q2 to the high level, and the high level potential Voff is sent to the differential amplifier 2 as the output signal SA from the sense amplifier 1.
Here, if the power source voltage is expressed as Vcc, and the threshold voltage of the MOSFET Q2 is expressed as VTP, the high level potential Voff can be obtained as; EQU Voff=Vcc-VTP (1)
As shown above, the sense amplifier 1 detects that the selected memory cell is in the conduction state or non-conduction state, and sends the potential Von or Voff, which is different in level from each other, as its output signal SA to the differential amplifier 2 in accordance with the state thus detected. The reference amplifier 3 sends the reference voltage Vref, which is set at a value between the potentials Von and Voff, to the differential amplifier 2 as its output signal RA. The differential amplifier 2 outputs the difference between the output signals SA and RA, namely, a signal OUT1 obtained by amplifying the potential difference between the signals Vref and Von or between the signals Vref and Voff.
FIG. 3 shows potential changes of respective components when a selected memory cell is changed from the conduction state to the non-conduction state due to the address change. If the selected memory cell is switched from the conduction state to non-conduction state, the electric potential SD of the connecting point 8 starts to be increased with a slight delay by charging, becoming a constant level soon. The output signal SA of the sense amplifier 1 is held at the low level potential Von for a short period of time and after lowered once, increased to the high level potential Voff. If the electric potential of the output signal SA exceeds the reference potential Vref, the output signal OUT1 of the differential amplifier 2 is changed from an electric potential of zero (low level) to the power source voltage Vcc (high level). In FIG. 3, also, a time t2 indicates a time interval from the time point when the selected memory cell is switched from the conduction state to the non-conduction state to the time point when the output signal OUT1 of the differential amplifier 2 starts to be risen.
However, as a practical semiconductor memory has memory cells arranged in a matrix pattern, the connecting point 8 of the row line or digit line is applied with load capacities such as the drain diffusion layer capacity and the like that respective memory cells have. Expressed by a numeric example, if the electric current supplying capacity of the P-channel MOSFET Q2 through the N-channel MOSFET Q1 is 0.2 mA in average, a load capacity applied to the connecting point 8 is 5 pF, and an electric potential of the input end 1a of the sense amplifier 1 when data are read out is 1 V, a time T1 to be taken for charging the electric potential of the connecting point 8 from 0 V to 1 V may be expressed as; ##EQU1##
With the conventional semiconductor memory shown above, in order to shorten a charging time T1, that is, in order to read out information speedily, for example, the mutual transconductance of the P-channel MOSFET Q2 may be enhanced. In this case, however, if doing as above, the potential amplitude between the low and high level potentials Von and Voff of the output signal SA of the sense amplifier 1 will become small, resulting in a problem that the detection of information becomes difficult.
In addition, if the power source voltage Vcc is lowered, the electric current supplying capacity of the P-channel MOSFET Q2 is reduced and the operation speed will be decreased. As a result, if the mutual transconductance of the P-channel MOSFET Q2 intends to be enhanced in order to compensate the speed-down, the detection of information is disadvantageously difficult as shown above.
Thus, an object of this invention is to provide a semiconductor memory in which the operation when the digit line is charged due to address change can be performed speedily and stably as well as the operated speedily even when a power source voltage is low.